The present invention relates to a semiconductor device, particularly to the interconnection structure of a semiconductor device realizing a reliable contact.
Electronic equipments of higher function, speed, and capacity require increased integration and more miniaturation of semiconductor devices. Particularly in DRAM devices, this is accomplished by reducing the surface area occupied by a unit cell. However, the reduction of the area occupied by the unit cell also diminishes cell capacitance, making it difficult to secure a sufficient charge in order to store the equivalent information of a less integrated device. To solve this problem of diminishing cell capacitance due to the reduction of the area occupied by the unit cell, various methods have been proposed for three-dimensional structures, which do increase cell capacitance, but on the other hand, aggravate the step between one element and the next, posing several other problems to solve.
A DRAM device includes a capacitor having a storage electrode, a dielectric film and a plate electrode, and a transistor having a source region, a drain region and a gate electrode (word line), all of which make up a unit cell. The DRAM requires a bit line to form a reliable contact with the drain region in order to transmit and store information. The bit line is formed after the formation of the transistor and capacitor, so as to overcome the difference of the step between the substrate where impurity diffusion regions such as source and drain regions are formed, and the capacitor's upper surface. Nevertheless, as a semiconductor memory device becomes more integrated, the requirement of storage capacitance per unit area increases. Thus, the height of the capacitor inevitably increases, accordingly, the step increases, and contrary to the goal, the end result is that the reliability of the bit line contacts decrease proportionally to the worsening of the step.
FIG. 1 is a cross section of the conventional interconnection structure of a semiconductor device. The above-described reliability decrease will be explained in more detail.
Referring to FIG. 1, two transistors share a common drain region 16, and each has a source region 14 and a gate electrode 18 on the active region of the semiconductor device substrate 10 which are divided into active and nonactive regions by a field oxide layer 12. Two capacitors C1 and C2 are formed in contact with the source region 14 of the transistors, and each includes a storage electrode 30, a dielectric layer 32 and a plate electrode 34. The above pair of transistors and capacitors constitute a pair of DRAM cell. An insulating layer 40 is formed for electrically isolating the cells, and a bit line 50 is formed to be in contact with drain region 16 by piercing the insulating layer 40. The bit line 50 is in contact with the drain region 16 via contact hole 9 which is as deep as the combined thickness of the capacitors C1 and C2 and the insulating layer 40.
If conductive material is deposited and patterned to form conductive layer on a semiconductor substrate with deep grooves, the conductive layer on the side walls and edges of the grooves is formed thinly or remains unformed altogether, which causes contact failures, stress migration, and/or electromigration, and deteriorates the reliability of the metallization. The contact failures and poor metallization reliability increase in proportion to the aspect ratio (height/width) of the contact hole.
Miniaturation of the memory cells is accomplished by reducing the impurity diffusion region (drain region 16) with which bit line 50 makes contact, and increasing cell capacitance by heightening the capacitors lengthens the depth of the contact hole 9 formed in insulating layer 40. A taller contact hole leads to a greater aspect ratio, thereby deteriorating the reliability of bit line contacts.